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1

An algorithm selection based platform for image understanding using high-level symbolic feedback and machine learning

Lukac, Martin, Kameyama, Michitaka

Journal:

International Journal of Machine Learning and Cybernetics

Year:

2015

Language:

english

File:

PDF, 1.70 MB

english, 2015

2

Asynchronous current-mode multiple-valued VLSI system based on two-color two-rail coding

Takahiro Hanyu, Michitaka Kameyama

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

2001

Language:

english

File:

PDF, 187 KB

english, 2001

3

Design of low-power quaternary CMOS logic circuits

Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1986

Language:

english

File:

PDF, 641 KB

english, 1986

4

[IEEE Distributed Processing Symposium (IPDPS) - Miami, FL, USA (2008.04.14-2008.04.18)] 2008 IEEE International Symposium on Parallel and Distributed Processing - FPGA implementation of a vehicle detection algorithm using three-dimensional information

Hariyama, Masanori, Yamashita, Kensaku, Kameyama, Michitaka

Year:

2008

Language:

english

File:

PDF, 432 KB

english, 2008

5

[IEEE 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012 - Seoul, Korea (South) (2012.05.20-2012.05.23)] 2012 IEEE International Symposium on Circuits and Systems - Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit

Xia, Zhengfan, Ishihara, Shota, Hariyama, Masanori, Kameyama, Michitaka

Year:

2012

Language:

english

File:

PDF, 582 KB

english, 2012

6

[IEEE 2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC) - Kaohsiung, Taiwan (2009.12.7-2009.12.9)] 2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC) - A Study of the Different Uses of Colour Channels for Traffic Sign Recognition on Hierarchical Temporal Memory

Melis, Wim J. C., Kameyama, Michitaka

Year:

2009

Language:

english

File:

PDF, 802 KB

english, 2009

7

[IEEE 2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC) - Kaohsiung, Taiwan (2009.12.7-2009.12.9)] 2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC) - Evaluation of Hierarchical Temporal Memory for a Real World Application

Melis, Wim J. C., Chizu, Shuhei, Kameyama, Michitaka

Year:

2009

Language:

english

File:

PDF, 377 KB

english, 2009

8

Recommendations for Impulse Voltage Testing

Hariyama, Masanori, Ogata, Sho, Kameyama, Michitaka, Morita, Yasutoshi

Journal:

Transactions of the American Institute of Electrical Engineers

Year:

1933

Language:

english

File:

PDF, 2.37 MB

english, 1933

9

[IEEE 2009 39th International Symposium on Multiple-Valued Logic - Naha, Okinawaw, Japan (2009.05.21-2009.05.23)] 2009 39th International Symposium on Multiple-Valued Logic - Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

Melis, Wim J.C., Chizuwa, Shuhei, Kameyama, Michitaka

Year:

2009

Language:

english

File:

PDF, 249 KB

english, 2009

10

Ferroelectric Non-Volatile Logic Devices

TAKASU, HIDEMI, FUJIMORI, YOSHIKAZU, NAKAMURA, TAKASHI, KIMURA, HIROMITSU, HANYU, TAKAHIRO, KAMEYAMA, MICHITAKA

Journal:

Integrated Ferroelectrics

Year:

2004

Language:

english

File:

PDF, 160 KB

english, 2004

11

[IEEE 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012 - Seoul, Korea (South) (2012.05.20-2012.05.23)] 2012 IEEE International Symposium on Circuits and Systems - FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators

Waidyasooriya, Hasitha Muthumala, Takei, Yasuhiro, Hariyama, Masanori, Kameyama, Michitaka

Year:

2012

Language:

english

File:

PDF, 1.16 MB

english, 2012

12

[IEEE 2019 International Conference on Information and Digital Technologies (IDT) - Zilina, Slovakia (2019.6.25-2019.6.27)] 2019 International Conference on Information and Digital Technologies (IDT) - Properties of Bent Functions in the Truth Domain

Lukac, Martin, Moraga, Claudio, Kameyama, Michitaka

Year:

2019

Language:

english

File:

PDF, 4.80 MB

english, 2019

13

Collision detection VLSI processor for intelligent vehicles based on ROM-type content-addressable memory

Masanori Hariyama, Michitaka Kameyama

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

1997

File:

PDF, 842 KB

1997

14

Optimal design of a VLSI processor with spatially and temporally parallel structure

Michitaka Kameyama, Masayuki Sasaki

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1997

File:

PDF, 810 KB

1997

15

A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects

Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama

Journal:

Systems and Computers in Japan

Year:

1997

File:

PDF, 934 KB

1997

16

Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application

Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama

Journal:

Systems and Computers in Japan

Year:

1998

Language:

english

File:

PDF, 3.40 MB

english, 1998

17

Design and evaluation of a digit-parallel multiple-valued content-addressable memory

Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama

Journal:

Systems and Computers in Japan

Year:

1998

Language:

english

File:

PDF, 2.62 MB

english, 1998

18

Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture

Yoshichika Fujioka, Michitaka Kameyama

Journal:

Systems and Computers in Japan

Year:

1999

Language:

english

File:

PDF, 339 KB

english, 1999

19

A field-programmable VLSI processor based on direct allocation of a control/data flow graph

Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

2004

Language:

english

File:

PDF, 2.01 MB

english, 2004

20

Recursive computation-based stereo matching and its implementation in VLSI

Kiyoshi Miura, Masanori Hariyama, Michitaka Kameyama

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

2004

Language:

english

File:

PDF, 1.25 MB

english, 2004

21

Road extraction VLSI processor based on optimal allocation and its application to highly safe intelligent vehicles

Masanori Hariyama, Takao Kudoh, Michitaka Kameyama

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

2004

Language:

english

File:

PDF, 1.74 MB

english, 2004

22

The 2 1Ag− state and two additional low-lying electronic states of spheroidene newly identified by fluorescence and fluorescence-excitation spectroscopy at 170 K

Yasutaka Watanabe, Tadayuki Kameyama, Yousuke Miki, Michitaka Kuki, Yasushi Koyama

Journal:

Chemical Physics Letters

Year:

1993

Language:

english

File:

PDF, 629 KB

english, 1993

23

Non-volatile one-transistor-cell multiple-valued CAM with a digit-parallel-access scheme and its applications

Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama

Journal:

Computers & Electrical Engineering

Year:

1997

Language:

english

File:

PDF, 530 KB

english, 1997

24

Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits

Michitaka Kameyama, Shugang Wei, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1990

Language:

english

File:

PDF, 717 KB

english, 1990

25

Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation

Takeshi Kasuga Member, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1990

Language:

english

File:

PDF, 805 KB

english, 1990

26

Design of a robust fault-tolerant multiplier

Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1991

Language:

english

File:

PDF, 566 KB

english, 1991

27

Performance evaluation of a multivalued rsa encryption vlsi

Shugang Wei, Michitaka Kameyama, Tatsuo Higuchi, Members

Journal:

Systems and Computers in Japan

Year:

1991

Language:

english

File:

PDF, 1021 KB

english, 1991

28

Design of an ultrahigher-valued biocomputing system based on set-valued logic networks

Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1992

Language:

english

File:

PDF, 728 KB

english, 1992

29

Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations

Shoui Kaqahito, Makoto Ishida, Tetsuro Nakamura, Kentaro Mizuno, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1993

Language:

english

File:

PDF, 1.02 MB

english, 1993

30

Sub-pixel edge location algorithm for bilevel images

Donghong Hu, Michitaka Kameyama, Xinmeng Chen, Ling Zhang, Lang Li

Journal:

Wuhan University Journal of Natural Sciences

Year:

2010

Language:

english

File:

PDF, 378 KB

english, 2010

31

Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits

Nobuhiro Tomabechi, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1986

Language:

english

File:

PDF, 558 KB

english, 1986

32

Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic

Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1987

Language:

english

File:

PDF, 833 KB

english, 1987

33

Design and implementation of an nmos image processor based on quaternary logic

Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1987

Language:

english

File:

PDF, 1.14 MB

english, 1987

34

Design of micropower CMOS quaternary memory circuits

Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1987

Language:

english

File:

PDF, 643 KB

english, 1987

35

Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation

Xi Yue Huang, Michitaka Kameyama, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1988

Language:

english

File:

PDF, 579 KB

english, 1988

36

Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System

Michitaka Kameyama, Li Zheng, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1988

Language:

english

File:

PDF, 671 KB

english, 1988

37

Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation

Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi

Journal:

Systems and Computers in Japan

Year:

1989

Language:

english

File:

PDF, 691 KB

english, 1989

38

Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model

Michitaka Kameyama, Takafumi Aoki Associate Member, Tatsuo Higuchi Member

Journal:

Systems and Computers in Japan

Year:

1990

Language:

english

File:

PDF, 715 KB

english, 1990

39

Protective effect of interleukin-6 against the death of PC12 cells caused by serum deprivation or by the addition of a calcium ionophore

Hiroyuki Umegaki, Kiyofumi Yamada, Michitaka Naito, Tsutomu Kameyama, Akihisa Iguchi, Toshitaka Nabeshima

Journal:

Biochemical Pharmacology

Year:

1996

Language:

english

File:

PDF, 713 KB

english, 1996

40

[IEEE 2013 IEEE 43rd International Symposium on Multiple-Valued Logic (ISMVL) - Toyama, Japan (2013.05.22-2013.05.24)] 2013 IEEE 43rd International Symposium on Multiple-Valued Logic - An Area-Efficient Multiple-Valued Reconfigurable VLSI Architecture Using an X-Net

Bai, Xu, Kameyama, Michitaka

Year:

2013

File:

PDF, 1.55 MB

2013

41

[IEEE 2011 16th Asia and South Pacific Design Automation Conference ASP-DAC 2011 - Yokohama, Japan (2011.01.25-2011.01.28)] 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) - An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

Komatsu, Yoshiya, Ishihara, Shota, Hariyama, Masanori, Kameyama, Michitaka

Year:

2011

Language:

english

File:

PDF, 230 KB

english, 2011

42

Architecture of a high-performance stereo vision VLSI processor

Hariyama, Masanori, Lee, Seunghwan, Kameyama, Michitaka

Journal:

Advanced Robotics

Year:

2000

Language:

english

File:

PDF, 158 KB

english, 2000

43

RFID-based localization with Non-Blocking tag scanning

Kashkouli Nejad, Keyvan, Jiang, Xiaohong, Kameyama, Michitaka

Journal:

Ad Hoc Networks

Year:

2013

Language:

english

File:

PDF, 1.08 MB

english, 2013

44

[IEEE 2013 IEEE 43rd International Symposium on Multiple-Valued Logic (ISMVL) - Toyama, Japan (2013.05.22-2013.05.24)] 2013 IEEE 43rd International Symposium on Multiple-Valued Logic - Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI

Bai, Xu, Kameyama, Michitaka

Year:

2013

File:

PDF, 1.32 MB

2013

45

[IEEE 2014 IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL) - Bremen, Germany (2014.5.19-2014.5.21)] 2014 IEEE 44th International Symposium on Multiple-Valued Logic - Analysis of Faults in Reversible Computing

Lukac, Martin, Kameyama, Michitaka, Perkowski, Marek, Kerntopf, Pawel, Moraga, Claudio

Year:

2014

Language:

english

File:

PDF, 295 KB

english, 2014

46

[IEEE 2011 11th International Conference on Intelligent Systems Design and Applications (ISDA) - Cordoba, Spain (2011.11.22-2011.11.24)] 2011 11th International Conference on Intelligent Systems Design and Applications - Non-blocking tag scanning for passive RFID localization

Nejad, Keyvan Kashkouli, Jiang, Xiaohong, Kameyama, Michitaka

Year:

2011

Language:

english

File:

PDF, 334 KB

english, 2011

47

Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path

Xia, Zhengfan, Hariyama, Masanori, Kameyama, Michitaka

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.35 MB

english, 2015

48

[IEEE 2013 International Soc Design Conference (ISOCC) - Busan, South Korea (2013.11.17-2013.11.19)] 2013 International SoC Design Conference (ISOCC) - A low-power FPGA based on self-adaptive multi-voltage control

Xia, Zhengfan, Hariyama, Masanori, Kameyama, Michitaka

Year:

2013

Language:

english

File:

PDF, 353 KB

english, 2013

49

[IEEE 2007 IEEE Asian Solid-State Circuits Conference - Jeju City, South Korea (2007.11.12-2007.11.14)] 2007 IEEE Asian Solid-State Circuits Conference - A Field-programmable VLSI based on an asynchronous bit-serial architecture

Masanori Hariyama,, Shota Ishihara,, Chang Chia Wei,, Michitaka Kameyama,

Year:

2007

Language:

english

File:

PDF, 449 KB

english, 2007

50

[IEEE 2013 International Soc Design Conference (ISOCC) - Busan, South Korea (2013.11.17-2013.11.19)] 2013 International SoC Design Conference (ISOCC) - Design and evaluation of a voltage-mode/current-mode hybrid logic circuit for a low-power fine-grain reconfigurable VLSI

Bai, Xu, Kameyama, Michitaka

Year:

2013

Language:

icelandic

File:

PDF, 597 KB

icelandic, 2013